FAQ

Getting started

Where can I learn about the HART protocol?


Porting HPAL

Can HPAL 2 be ported to a different processor or compiler?.

 

HART Specifications

Where can I get the HART Protocol specifications?


HCF Membership

Do I have to become a member of the HART Communication Foundation?


HART Master

Can HPAL2 be used to build a HART master?


Footprint

How much memory does HPAL2 require?


SLOC

How many Source Lines of Code is HPAL2?


Documentation

How is the software documented?

 

Exalon Delft HART® 7.6

Wired Slave Stack HPAL2

HPAL2 is the Exalon Delft HART V7.6 Slave Protocol stack for wired slave devices.

COMPLETE

HPAL2 implements everything you will reasonable need for the communication layer of your wired HART device and even for your wirelessHART maintenance port.

HPAL2 allows you to focus on your domain specific knowledge.

Best tested

HPAL2 passes all tests from the HCF Test Specifications as implemented by the HCF HART Test System (HCF_KIT-192 upd 3.2)*.


And what's more: it passes all tests implemented by the Exalon Delft HART Test Bench, the most comprehensive HART test tool on the market. HART Test Bench implements all relevant tests for which the HCF has defined test specifications, and implements these even more strictly to reduce the change of false positive test results.


You need to be sure your device conforms to HCF specifications? This is as sure as it gets.

Supported Hardware platforms

HPAL2 is distributed with 3 fully working example applications. Two for the Renesas M16 platform (M16C/62p and M16C/63) and one for ARM (STM32L on a Discovery board).

HPAL2 has been developed especially with the Renesas M16C family in mind. In combination with Renesas C compiler and On-chip debugger. You can development of your software directly on your hardware platform without expensive emulators or other specialized hardware that may interfere with your platforms power or start-up behavior. Special On-Chip facilities offered by the Renesas M16C family in combination with the software design of HPAL2 make the On-chip debugger kernel virtually invisible to your code.


The M16C family has traditionally been the obvious low-power high performance choice for fieldbus protocol stacks like Profibus PA and Foundation Fieldbus and is the only processor to date to simultaneously support all major fieldbusses with high-quality stacks.


Nevertheless you can select any other low-power microcontroller and easily port the code. The little hardware dependent code is separated into one module to make porting as straightforward as possible. With the three examples you are immediately up to speed.

The importance of timing

To achieve reliable HART communication it is extremely important that the timing of incoming and sent characters and messages precisely follow the specifications of the protocol. Specifically the timing between 2 sent or received characters must be strictly observed. Generic HART protocol stacks demand the highest interrupt priority for the processing of communication, which complicates the interrupt handling of the application.


While in past applications of HART communication was almost always point-to-point, in current multi-drop networks with WirelessHART gateways, multiple masters and bursting devices these timing aspects are particularly important as the reliability of the net works and it's ability to recover from faults depend on it.

 

On the M16C family HPAL2 uses built-in peripherals (RTS handshake, DMA) to there fullest extent, minimizing interference with the interrupt handling of your application or that of the software debugger. On other platforms these functions can be implemented in software as required.

Energy efficient architecture

HART devices typically have less than 1 mA current available for the microcontroller. Advanced hardware designs can store excess currents for use during computationally intensive periods. HPAL2 makes this easy with an event driven architecture, where all code runs in interrupt handlers. This way the main loop contains only one instruction: IDLE. As wake up from idle is automatic (on M16C platforms) the result is that the processor only runs when an interrupt occurs and maximum power efficiency is obtained.

Application Layer

HPAL2 implements a complete HART Application Layer based on a Generic Transducer Model. This means you start with a working transmitter that already complies with the HART V7 slave specifications.

 

The following table shows the functions that HPAL2 implements:

 

HPAL2 Functionality
Feature Support
HART Conformity V 7.6
Data Link Layer Universal Commands Yes
Universal Commands Yes
Dynamic Variables Yes
Device Variables Transducer Model based
Dynamic Variable Mapping Yes
Standardized Device Variables Yes
Abstracted Sensor Yes
Hart Device Status Yes
Extended Field Device Status Yes
Multi Slave Address Mode Yes
Analog Channels implementation Yes
Block Transfer Yes
Trimming Yes
PV Ranges/Transfer Function/Damping/Alarm Yes
Device Variable Damping/Span/Limits Yes
Device Variable Information/Classification/Family Yes
Device Self Test and Reset Yes
Configuration Changed Reset Yes
Device Variable Set Zero Yes
Device Variable Write Units Yes
Device Locking Yes
Device Variable Value writing Yes
Device Variable Catching Yes
Multiple Burst Messages Yes
Burst Triggers and Periods Yes
Smart Data Publishing and Event Notification Yes
Time stamped Data and Real Time Clock Yes
Aggregated Commands Yes
Device Location and Locale Yes
Persistence Maintenance (erase, compact) Yes
Namur NE107 Yes
Condensed Status Map Yes
Status Simulation Yes
Delayed Response Mechanism Yes

 


Supported HART Commands

Hide table listing HART commands supported by HPAL2.

 

HART Commands implemented by HPAL
Category Number Description
Universal Commands 0 Read Unique Id
1 Read Primary Variable
2 Read Loop Current and Percentage of Range
3 Read Dynamic variables and Loop Current
6 Write Polling Address
7 Read Loop Configuration
8 Read Dynamic Variable Classifications
9 Read Device Variables with Status
11 Read Unique Id Associated with Tag
12 Read Message
13 Read Tag, Descriptor and Date
14 Read Primary Variable Transducer Information
15 Read Device Information
16 Read Final Assembly Number
17 Write Message
18 Write Tag, Descriptor and Date
19 Write Final Assembly Number
20 Read Long Tag
21 Read Unique Id Associated with Long Tag
22 write Long Tag
38 Reset Configuration Changed Flag
48 Read Additional Device Status
Common Practice Commands 33 Read Device Variables
34 Write PV Damping Value
35 Write PV Ranges
36 Set PV Upper Range
37 Set PV Lower Range
40 Enter/Exit Fixed Current Mode
41 Perform Self Test
42 Perform Device Reset
43 Set Primary Variable Zero
44 Write PV Units
45 Trim Loop Current Zero
46 Trim Loop Current Gain
47 Write Primary Variable Transfer Function
49 Write Primary Variable Transducer Serial Number
50 Read Dynamic Variable Assignment
51 Write Dynamic Variable Assignment
52 Set Device Variable Zero
53 Write Device Variable Units
54 Read Device Variable Information
55 Write Device Variable Damping Value
56 Write Device Variable Transducer Serial Number
59 Write Number of Response Preambles
60 Read Analog Channel And Percentage Of Range
62 Read Analog Channels
63 Read Analog Channel Information
64 Write Analog Channel Additional Damping Value
65 Write Analog Channel Range Values
66 Enter/Exit Fixed Analog Channel Mode
67 Trim Analog Channel Zero
68 Trim Analog Channel Gain
69 Write Analog Channel Transfer Function
70 Read Analog Channel Endpoint Values
71 Lock Device
72 Squawk
73 Find Device
76 Read Lock Device State
78 Read Aggregated Command
79 Write Device Variable
80 Read Device Variable Trim Points
81 Read Device Variable Trim Guidelines
82 Write Device Variable Trim Point
83 Reset Device Variable Trim
89 Set Real Time Clock
90 Read Real Time Clock
100 Write Primary Variable Alarm Code
103 Write Burst Period
104 Write Burst Trigger
105 Read Burst Mode Configuration
106 Flush Delayed Responses
107 Write Burst Device Variables
108 Write Burst Command Number
109 Write Burst Mode Control
111 Transfer Service Control
112 Block Transfer
113 Catch Device Variable
114 Read Caught Device Variable
115 Read Event Notification Summary
116 Write Event Notification Bit Mask
117 Write Event Notification Timing
118 Event Notification Control
119 Acknowledge Event Notification
512 Read Country Code
513 Write Country Code
516 Read Device Location
517 Write Device Location
518 Read Location Description
519 Write Location Description
520 Read Process Unit Tag
521 Write Process Unit Tag
523 Read Condensed Status Mapping Array
524 Write Condensed Status Mapping
525 Reset Condensed Status Map
526 Write Status Simulation Mode
527 Simulate Status Bit

 


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FAQ

Getting started

The HART communications foundation has an "Application Guide" available at no cost (PDF download). Further you can purchase "HART Field Communications Protocol – A Technical Overview". This document provides an excellent starting point to understand HART specifications and HPAL2 code.

Can HPAL2 be ported to a different processor or compiler?

Yes, the little hardware dependent code is separated into one module to make porting as straightforward as possible. The Renesas compiler used is ANSI C with a few extensions found in most other embedded microcontroller compilers. Exalon Delft can support you with the porting process and validate your results if you desire.

Where can I get the HART Protocol specifications?

Please see the Specifications & Documents page of the HART Communication Foundation or the International Electrotechnical Commission website.

Do I have to become a member of the HART Communication Foundation?

Not necessarily, but we recommend that you do.

The HART Communication Foundation holds certain Intellectual Property rights like trademarks, copyrights and patents. Becoming a member gives you certain rights to make use of this IP. Vice-versa the HART Communication Foundation defends these rights on behalf of it's members.

If you remove the parts of the stack that might be protected by IP rights (like Burst Mode), don't use HCF trademarks and purchase specification documents separately you might not need to be come a member. If in doubt about these matters contact the HCF directly or seek professional legal advice.


Can HPAL2 be used to build a HART master?

You can change any software into any other software. But realistically, a HART master is a completely different state machine then a HART slave. If you need a master you might consider our Smart HART Modem which has a built-in master.

How much memory does HPAL2 require?

This will depend a lot on what your device implements, like the number of Device Variables etc., as well as on you hardware platform and compiler.

The sample application using the Generic Transmitter model and having full bursting support, built on an M16C platform uses about 4K RAM and 48.5K ROM.

How many Source Lines of Code is HPAL2?

All source lines combined measured using sloccount tool amounts to SLOC of 12K which corresponds to 2.8 Person-Years of programming and testing.

How is the software documented?

The software is self documenting (Doxygen). In addition we have a software manual included. All documentation provided does not replace, and is intended to be read in conjunction with, protocol design analysis, specification and test documentation as provided by the HART Communications Foundation.


*Some tests implementations of the HCF Test System are erroneous or not yet up-to-date with HART revision 7.6. This has been reported to the HCF.